Conventionally, as seen from FIG. 1, a scanning conversion circuit comprises a 262H delayer 12, a 1H delayer 14, a 262H delayer 16, adders 18 and 20, a constant multiplier 22, coefficient-variable constant multipliers 24 and 26, a movement detecting section 28 and a double-speed converting section 36.
The movement detecting section 28 detects the movement of the image on the bases of the video signal Vi (e.g., video signal according to the NTSC system) for the interlace scanning inputted to the input terminal 10, and the signal delayed by 525H (1H represents 1 line, and 525H is equivalent to the delay by 1 frame) by means of the 262H delaying section 12, 1H delaying section 14 and 262H delaying section 16. More specifically, the signals of the detected movement (1−K) and K, which become K=0 in the case of the moving image and K=1 in the case of the still image.
The adder 18 adds the output signal of the 262H delayer and the output signal of the 1H delayer 14, and the constant multiplier 22 multiplies the output signal of the adder 18 by the coefficient ½. Therefore, the constant multiplier 22 outputs the video signal obtained by averaging the video signals of the upper scanning line and the lower scanning line to the interpolated scanning line. This video signal corresponds to the video signal for the in-field interpolation processing.
One of the coefficient-variable constant multipliers 24 and 26 multiplies the video signal, which has been delayed by 1 field by means of the 252H delaying section (the video signal for interfield interpolation processing), by the signal detected by the movement detecting section 28 and outputs the result, while the other constant multiplier 26 multiplies the output signal of the constant multiplier 22 by the detected signal (1−K) from the movement detecting section 28 to output the result.
The adder 20 adds the output signal of the constant multiplier 24 and the output signal of the constant multiplier 26 to obtain the video signal (the video signal of the interpolation signal) for the interpolated scanning line.
Therefore, since K=0 in the case of a moving image, the coefficients of the constant multipliers 24 and 26 becomes 0 and 1, so that only the video signal, obtained by averaging the video signals of the upper adjacent scanning line and the lower adjacent scanning line, is outputted from the adder 20, and since K=1 in the case of the still image, the coefficients of the constant multipliers 24 and 26 are reversed to become 1 and 0, whereby only the video signal preceding by 1 field is outputted from the adder 20.
For instance, in the case of a moving image, the video signal of the interpolation point Np of the interpolated scanning line becomes the signal obtained by averaging the video signals of the sampling points Sp and Sp in the vertical direction from the upper and lower adjacent scanning lines, while, in the case of a still image, as indicated by the arrow followed by the dotted line, the signal becomes the video signal of the sampling point Sp corresponding to the field (n−1) preceding by 1 field.
The double speed converting section 36 is capable of performing double speed conversion processing by using a double-speed clock in reading out the video signal Vi, delayed by 263H by means of the 262H delaying section 12 and the 1H delaying section 14, and the output signal of the adder 20, which have been stored in the memory, to output the video signal Vp for progressive scanning.
The double speed converting section 36, for example, though not limited to this example, comprises a first memory (e.g., a line memory) for storing the video signal outputted from the 1H delaying section 14 and a second memory (e.g., a line memory) for storing the video signal of the interpolated scanning line outputted from the adder 20, whereby the video signal Vp for progressive scanning is outputted from the output terminal 38 by reading out the data stored in the first and the second memories alternately for each 1 line by using the double-speed clock.
However, the conventional scanning conversion circuit shown in FIG. 1 has a drawback in that the inclined lines in the moving image appear unnatural.
For instance, when the inclined line 40 having 2-dot width appears in the moving image, the two interpolation points Np1 and Np2 included in the inclined line 40 of the interpolated scanning line becomes the signal obtained by averaging the video signals of the sampling points Spb and Spc of the upper scanning line and the sampling points Spe and Spf of the lower scanning line. In consequence, the interpolation points Np1 and Np2 have a half-lighted state (gray color between block color and white color) despite being required to have a lighted state (white color), and the outer two interpolation points Np3 and Np4 have a half-lighted state despite being required to have a non-lighted state (block color), thereby causing a problem that these interpolation points look unnatural.
The present invention is made in consideration of the above-mentioned problem and is intended to provide a scanning conversion circuit capable of preventing the vertical line and inclined lines in the moving image from appearing unnatural and reproducing a high-quality image when the moving image is displayed on the basis of a video signal (e.g., a video signal for progressive scanning) which has undergone scanning conversion processing.